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Tool Flows
3
SmartDesign
CorePCIF is available for download to the SmartDesign IP Catalog, via the Actel Libero? Integrated Design
Environment (IDE) web repository. For information on using SmartDesign to instantiate, configure, connect, and
generate cores, refer to the Libero IDE online help.
The core can be configured using the configuration GUI within SmartDesign, as shown in Figure 3-1 on page 30
through Figure 3-3 on page 32 . “General Configuration Parameters” on page 35 explains the configuration parameters
and their recommended values .
Synthesis in Libero IDE
To run Synthesis on the core, set the design root to the top of the project . This is a wrapper around the core that sets all
the generics appropriately.
Make sure the required timing constraints files are associated with the synthesis tool. There should be four timing
constraints files available, covering 33/66 MHz and 32-/64-bit operation:
pcitiming32_33_synplicity.sdc
pcitiming32_66_synplicity.sdc
pcitiming64_33_synplicity.sdc
pcitiming64_66_synplicity.sdc
Appendix B on page 137 details the timing constraints that are required.
Click the Synthesis icon in Libero IDE. The synthesis window appears, displaying the Synplicity? project. To run
Synthesis, click the Run icon.
To allow the core to be synthesized standalone within Libero IDE, an additional top-level module, PCICORETEST, is
also imported into Libero IDE. The top level only includes the PCI bus signals; all the core backend signals are
connected to a loopback module. This allows the core to synthesized and place-and-route performed in small-pin-count
packages so that utilization and performance can be verified without user logic being connected to the backend interface.
To use this top level, the design root must be set to PCICORETEST in Libero IDE.
Additionally, the PCISYSTEM or PCISYSTEM2 stimulus file can be moved to the HDL directory; these files add fully
functioning memory and FIFO to the backend of the core (Axcelerator, IGLOO/e, ProASIC3/E/L, and Fusion FPGA
families only), creating a single-chip PCI system (see “User Testbench” on page 121 ). To synthesize the PCISYSTEM
design, move the pcisystem , fifo , memory , ram2k8 , and fifo512x32 files from the CorePCI stimulus directory to the HDL
source files directory in Libero IDE, and then set the design root to PCISYSTEM . For the PCISYSTEM2 design,
move the pcisystem2 , memory , and ram2k8 files.
v4.0
29
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相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
CP2-GSA-L CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1 CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4 CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F COMPACT PCI - MISC
CP2105EK KIT EVAL FOR CP2105
相关代理商/技术参数
COREPCIF-RMFL 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPRO LEDBULB 10.5-60W B 制造商:Philips Lumileds 功能描述:
COREPRO LEDBULB 10.5-60W E 制造商:Philips Lumileds 功能描述: